Parasitic-aware optimization of CMOS RF circuits /
In the arena of Parasitic-Aware Design of CMOS RF Circuits, efforts are aimed at the realization of true single-chip radios with few, if any, off-chip components. Ironically, the on-chip passive components required for RF integration pose miore serious challenges to SOC integration than the active C...
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Format: | eBook |
Language: | English |
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Boston :
Kluwer Academic Publishers,
[2003]
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Online Access: | Connect to the full text of this electronic book Connect to the full text of this electronic book |
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100 | 1 | |a Allstot, David James. |0 http://id.loc.gov/authorities/names/n86856098 | |
245 | 1 | 0 | |a Parasitic-aware optimization of CMOS RF circuits / |c by David J. Allstot, Kiyong Choi, Jinho Park. |
264 | 1 | |a Boston : |b Kluwer Academic Publishers, |c [2003] | |
264 | 4 | |c ©2003 | |
300 | |a 1 online resource (xvii, 162 pages) : |b illustrations | ||
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504 | |a Includes bibliographical references and index. | ||
588 | |a Description based on print version record. | ||
520 | |a In the arena of Parasitic-Aware Design of CMOS RF Circuits, efforts are aimed at the realization of true single-chip radios with few, if any, off-chip components. Ironically, the on-chip passive components required for RF integration pose miore serious challenges to SOC integration than the active CMOS and BJT devices. This is not surprising since modern digital IC designs are dominated as much, or more, by interconnectg characteristics than by active device properties. In any event, the co-integration of active and passive devices in RFIC design represents a serious design problem and an even more daunting manufacturing challenge. If conventional mixed-signal design techniques are employed, parasitics associated with passive elements (resistors, capacitors, inductors, transformers, pads, etc.) and the package effectively de-tune RF circuits rendering them sub-optimal or virtually useless. Hence, dealing with parasitics in an effective way as part of the design process is an essential emerging methodology in modern SOC design. The parasitic-aware RF circuit synthesis techinques described in this book effectively address this critical problem. | ||
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650 | 0 | |a Radio circuits |x Design and construction. |0 http://id.loc.gov/authorities/subjects/sh2010109336 | |
650 | 0 | |a Transients (Electricity) |x Prevention. | |
650 | 0 | |a Very high speed integrated circuits |x Design and construction. | |
650 | 0 | |a Metal oxide semiconductors, Complementary |x Design and construction. |0 http://id.loc.gov/authorities/subjects/sh2008107701 | |
650 | 0 | |a Systems on a chip. |0 http://id.loc.gov/authorities/subjects/sh2002000568 | |
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650 | 7 | |a TECHNOLOGY & ENGINEERING |x Mobile & Wireless Communications. |2 bisacsh | |
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700 | 1 | |a Choi, Kiyong. |0 http://id.loc.gov/authorities/names/n2003005601 | |
700 | 1 | |a Park, Jinho. |0 http://id.loc.gov/authorities/names/n2003005602 | |
710 | 2 | |a SpringerLink (Online service) |0 http://id.loc.gov/authorities/names/no2005046756 | |
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