Principles of verifiable RTL design : a functional coding style supporting verification processes in Verilog /
Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improveme...
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Format: | eBook |
Language: | English |
Published: |
Norwell, Mass. :
Kluwer Academic Publishers,
[2000]
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Online Access: | Connect to the full text of this electronic book Connect to the full text of this electronic book |
Internet
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Call Number: |
TK7874.75. B47 2000eb |
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Call Number | Status | Get It |
TK7874.75. B47 2000eb | Available |